Research On Quantization Noise Optimization Technology Of Phase-locked Loop Based On Time Domain Method

With the progress of science and technology,people have higher and higher requirements on the performance of electronic system,such as working speed and noise.As a common frequency synthesis technology,phase-locked loop(PLL)can provide the required clock frequency for each module in the circuit system.It is the heart of all electronic products.Its operating frequency,phase noise and other indicators directly determine the performance of the system.Therefore,the design of PLL with high frequency and low noise has always been the focus of researchers at home and abroad.In order to break through the limitations of integer-N PLL in terms of frequency modulation resolution and loop bandwidth,fractionalN PLL based on delta-sigma modulator(DSM)has been widely used,which achieves the mixed fraction multiple frequency division of the input signal by means of periodic averaging,and thus improving the flexibility of the reference signal and the divider.However,due to the quantization error of instantaneous integer-N,a large amount of quantization noise will be introduced into the system.Therefore,it results in the reduction of the purity of the output spectrum,which limits fractional-N PLL in the application scenarios with high precision.Therefore,researchers have proposed several quantization noise optimization methods based on analog compensation or digital filtering.In this thesis,a quantization noise optimization circuit using phase interpolator digital-to-time converter(DTC)based on time domain method is proposed to solve the problem caused by quantization error in the fractional-N PLL structure.Firstly,the working principle and phase noise of factional-N PLL are analyzed in detail in this thesis.The mechanism of quantization noise is researched,and the existing quantization noise optimization technologies are compared.Secondly,the quantization noise optimization method based on DTC circuit is researched emphatically,and the limitations of traditional DTC in resolution and linearity are analyzed.Then,an all-digital phase interpolator circuit is designed and a DTC based on it is built.The DTC can satisfy both high delay linearity and high delay resolution,and has advantages of simple control logic,standardness and simple parameter adjustment,which is suitable for high-precision compensation of the quantization error of fractional-N PLL.Finally,the fractional-N PLL containing quantization nose optimization circuit is constructed,and a corresponding time domain compensation algorithm is designed.According to the simulation results,the optimized effect of the designed DTC circuit on quantization noise is verified from the perspective of time domain and frequency domain.The circuit construction and simulation are based on Cadence platform.According to the layout simulation results of 64-bit phase interpolator DTC in 40 nm process,the average delay resolution of 64-bit DTC can achieve 44.118 fs.The absolute value of differential nonlinearity(DNL)is less than 1.5 fs,and the absolute value of integral non-linearity(INL)is less than 3 fs.According to the chip test results,the absolute value of fine-tuned DNL is less than 10 fs,and the absolute value of fine-tuned INL is less than 9 fs.In order to verify the optimization of quantization noise,the phase interpolator DTC was implanted into the fractional-N PLL of 180 nm process.According to the simulation results,the frequency fluctuation range obtained by inverting the period of PLL output signal after locking is reduced from 0.1 MHz to 0.03 MHz from the perspective of time domain.From the perspective of frequency domain,with the help of DTC based on phase interpolator circuit,the frequency component caused by quantization error is greatly reduced,and the background noise is reduced by 10 d B.The results prove the correctness and validity of the research.