Techniques For Evaluating Single-Event Effect In SRAM-based FPGAs

Single-Event Upset in SRAM-based FPGAs is an important threat for spaceelectronic systems. The upsets in FPGA's configuration memory may alter circuitstructures and lead to persistent functional error. This phenomenon is much morecomplicated than upsets in traditional memory devices. How to evaluate this kind ofeffect has become a major concern. The contributions of this paper include:(1) A two-layer model is proposed. The static upset cross section of physical layeris adopted to describe the sensitivity of different device series, and the dynamic crosssection of application layer is used for predicting the system failure rate on certain orbits.The concept of sensitive bits is defined to build a connection between the two crosssections, as well as the results of irradiation test and simulation methods.(2) The hardware and software platform is developed for testing radiation effectsin SRAM-based FPGAs. The internal memory upsets, circuit function and powercurrent can be monitored during the irradiation test. Accelerator experiment has beendone on HI-13. The static cross sections for several device series were measured and thedynamic Single-Event behaviors for some benchmark circuits were also studied.(3) Due to the limitation of beam time and expense, it is not wise to assess thereliability for systems implemented on SRAM-based FPGAs using accelerators. A faultinjection system is established to simulate SEUs in FPGA's configuration memory. Thismethod is able to find all the sensitive bits in a certain design. Therefore, it can be usedto predict the dynamic cross section and verify the effectiveness of redundant strategies.(4) JBits SDK is adopted to decode the bitstream of Xilinx Virtex FPGA series.The decoded results find the relationship between programmable structures andaddresses in the bitstream. It also identifies different failure modes induced by SEUs,which constitutes the basis of soft error analysis tool in the following sections.(5) A soft error analysis tool is proposed. The structures inside an FPGA aremodeled using Objective-Oriented way. The programs read in the netlist of circuitdesigns to get the configured resources and their logic states, and search for all thecritical nodes and routings which might destroy the circuit structure. The sensitive bitscan be queried from the database containing the decoded results.