.100 G Ethernet Pcs Sublayer And Its Fpga Implementation

The rapid development of video services led to a sharp increase in demand for network bandwidth,so that backbone bandwidth is facing more and more presure of growing bandwidth.In addition, Ethernet-based telecom applications has exacerbated such a situation.Today, single-channel 100Gb/s transmission technology has emerged, suggesting 100G transmission time has come.100 Gigabit Ethernet (100GE, 100 Gigabit Ethernet) is the latest Ethernet technology, which is not only 10 times faster than 10 Gigabit Ethernet at rate , but it has also been further expanded in the application scope. 100GbE applies not only to all the traditional Ethernet applications, but also to the MAN and the WAN.The implementation of IEEE802.3 100G Ethernet PCS (Physical Coding Sublayer) function is designed based on Xilinx's FPGA in this dissertation. The 100G Ethernet and functions and key technologies about the PCS over 100G Ehternet is introduced firstly. Then it focuses on the PCS Sub-layer FPGA design and implementation, simulation and testing.Multi-channel distribution (MLD) mechanism is introduced in the project. PCS sub-layer distrubutes encode data to multiple logical channels which are called virtual channels, to solve the adaptation problem for different physical channels or light wavelength in the present technologies and production conditions .MLD mechanism is the key mechanism in the paper.Based on the theory of the scrambling, a parallel self-synchronizing scrambling algorithm is studied in this paper.And gained a parallel framer synchronous scrambling. This algorithm uses a recursive method to calculate the logic relationship of the scrambler.It is faster ,more simple and very easy to be implemented by handware.Finally 640bits parallel self-synchronizing scrambling algorithm is implemented on FPGA in the 100G Ethernet.Top_down design method is used in this project.First of all the master plan, including the architecture of the system, the module dividing, the design method and the coding style is expatiated. After that, the detail of each module with testing data results and the timing simulation waveform are given out.VerilogHDL is used for this project. The core's synthesis, place route and assemble was based on develop tool Xilinx ISE 9.2.03i. The timing simulation was based on QuestaSim. At last, design module is downloaded in develop kit upon which real-time simulation was done to analyse the waveform.While constructing the system, wo spent a lot of time to consider how to divide and define each module and how to coordinate and interconnect these modules. When designing the code, we payed much attention to hardware resource spending and concurrent executable ability of the VerilogHDL language to make the design close to the hardware working way, so we could gain a high speed with a low hardware spending to satisfy the demand of the cost, performance and practicability.