200G Ethernet PCS Sublayer Circuit Design

The 200 G Ethernet standard IEEE 802.3bs improves the Physical Coding Sublayer(PCS)on the basis of 100 G Ethernet.Inserting alignment marks in a single channel is modified to insert the alignment mark group into the main channel uniformly,simplifying the way of inserting alignment marks.When the receiving end is synchronized,the sync header search is deleted,and only the alignment mark is locked.The forward error correction function has been added to facilitate error correction when receiving data.By studying the structure and function of the PCS sublayer in the IEEE 802.3bs standard,and combining a large number of 100 G Ethernet PCS sublayer implementations,an overall design plan for the 200 G Ethernet PCS sublayer is proposed.The principle of 64B/66 B encoding and decoding is analyzed in detail,and a 4-channel parallel 64B/66 B codec is designed,which can complete 4 encoding and decoding in one clock cycle,which improves the efficiency of encoding and decoding.In-depth analysis and refinement of the 256B/257 B transcoding and re transcoding rules,detailed 257-bit parallel de-scrambling formula deduced.The gearbox module is added to realize the bit width conversion between 257-bit parallel data and2*320-bit parallel RS(544,514)codec.The PCS sub-layer sending module uses the alignment mark mapping function to create an alignment mark group and inserts the data stream,and then distributes the alignment mark to each channel correctly through two 10-bit round-robin distributions in the Pre-FEC module and the channel interleaving distribution module.The PCS receiver first locks the alignment mark on a single channel,and after all the channels are locked,the deskew and rearrangement are performed uniformly to complete the channel synchronization of the receiver.Completed the design of the 200 G Ethernet PCS sub-layer circuit.During the loopback test,a channel disturbance module that simulates the delay and disorder behavior of the PCS receiving end was inserted between the sending module and the receiving module,and the PRBS15 pseudo-random code packet transmitter was used Generate test stimuli.The circuit function is simulated by software VCS and Verdi,and finally the circuit is verified by FPGA.The simulation and verification results show that the design can realize the logic function of the 200 G Ethernet PCS sublayer.The functional design,simulation,and verification of the 200 G Ethernet PCS sublayer realized in this thesis have important reference value for the study of the 200G/400 G Ethernet PCS sublayer.