A Routing Control Interface On FPGA Between RapidIO And 10 Gigabit Ethernet

With the development of information technology, the demand for good instantaneity and high reliability of computer technology is growing. And thanks to the progress of chip technology, embedded computing technology is enjoying broad space for development and application prospect. At the moment, embedded computing technology has got into many fields including industrial control, environmental engineering, information household appliance and personal communication product. Especially high-performance embedded computing technology, which is playing important roles in focused areas such as national defense and aerospace. The development of high-performance embedded distributed cluster system cannot be separated from the development of high-speed bus. In integrated information processing system, which is built by high-performance embedded computing technology, serial RapidIO high-speed bus and 10 Gigabit Ethernet are used separately in front-end RF preprocessing and back-end integrated display control processing as data exchange networks to realize high-speed communication of data. Therefore, real-time data conversion between the two protocols has become a serious problem.Serial RapidIO adopts high-speed serial communication technique, and could be used for multi-processor interconnection, computer cluster system, cloud computing and memory sharing. It is widely used in the interconnection between the chips and interconnection on board. Presently, in the field of embedded computing and communication technique, RapidIO has become the first choice of interconnection of new type multi-computer, multi-processor and multi-DSP.10 Gigabit Ethernet is a kind of high-speed Ethernet interface, which could provide long-distance transmission and the bandwidth could reach lOGbps. It is widely used in situations where needs high data bandwidth like data-switching center and digital video broadcast. And it could realize large data volume aggregation and link aggregation efficiently on the net.In this paper, a routing control interface between Serial RapidIO and 10 Gigabit Ethernet is designed, aiming at real-time data conversion between the two protocols. The interface is a high-speed real-time data transmission channel, realized by hardware design technique. It could be widely used in integrated electronic information system, or be used as intelligent IO interface module in front-end RF preprocessing and core processor platform to solve the real-time big data exchange problem in real-time embedded system and back-end task information processing system. The routing control interface has high application value.The main work of this paper includes:(1) A routing control interface based on FPGA between Serial RapidIO and 10 Gigabit Ethernet is designed in this paper. Pipeline operation is used to speed up data package conversion between the two protocols. This interface is composed of a 4×SRIO interface, a 10 Gigabit Ethernet interface and a user scheduling logic module. Among them the user scheduling logic module has two parts of main function:should two the process:one is to receive data packages from 10 Gigabit Ethernet interface and then convert them into RapidIO mailbox messages; the other one is to receive RapidIO mailbox messages and then convert them into Ethernet packages.(2) RapidIO mailbox message mechanism is used to realize the data conversion between different protocols. Ethernet packages are split into several groups of message segments, while RapidIO mailbox messages are united into Ethernet packages to be sent. RapidIO Doorbell is used as an interrupt to notify receiver of the completion of a transmission. In both direction of 10G Ethernet to RapidIO and RapidIO to 10G Ethernet, message transmission construct that could retransmit packages with time-out error is adopted.(3) When RapidIO mailbox messages are being processed, the received messages will be stored inside the FPGA. They won’t be transmitted until one group of messages has been assembled. In order to differ the content of the messages from other messages,16 mailbox modules are designed to hold and organize several groups of messages in same time. Message length (Msglen) and message segment flag (Msgseg) are used to check whether a whole group of messages has been received.(4) Physical address and mailbox address LUT is generated and put in register block to store the match information between 10 Gigabit Ethernet devices and RapidIO mailboxes. In the same time, RapidIO NREAD and NWRITE operations are used to maintain and rewrite the registers.