Research On Single Event Upset Mitigation Techniques For SRAM-based FPGA In Space Imaging System

In recent years,with the continuous development of China's aerospace technology,SRAM-based FPGAs have been widely used in the field of space imaging because of superior performance and reprogramming advantage,such as space surveillance and remote sensing imaging.However,due to the complex radiation environment and the limitation of SRAM-based FPGA's own structure and manufacturing process,it is very vulnerable to high-energy particles in the space,which may probably trigger Single Event Upset(SEU).SEUs may result in function interrupt and the image data lost in the imaging system,which is related to the efficient completion of the space mission.Therefore,research on the SEU mitigation technology for SRAM-based FPGAs has become a major difficulty and hot issue in the aerospace field.In order to improve the ability of correcting SEUs in spatial imaging system,this thesis uses a combination of Three-Mode Redundancy(TMR)and Scrubbing to improve the reliability of the imaging system,after researching various SEU mitigation techniques.The specific design is divided into the following sections.(1)The design of system hardware experimental platform.This thesis designs a circuit with double SRAM-based FPGAs based on space imaging applications,and builds an experimental verification platform for SEU mitigation techniques.Including device selection,schematic design and eight-layer PCB drawing.Based on this platform,a semi-physical simulation verification method is used to study the principle and effect of SEU mitigation techniques.This system mainly realizes the driving timing design of the CCD camera,as well as the configuration,scrubbing and readback operation of the SRAM-based FPGA.(2)The design of SEU mitigation scheme.This thesis proposes two SEU mitigation techniques,the first scheme is scrubbing combines TMR,and the second is readback combines TMRT.Taking the Virtex-II series FPGA XC2V3000 as an object,researching the structure of the configuration memory area,as well as the principle and process of configuring,scrubbing,and readback operation.The Verilog hardware language is used to design the related logic codes.At the same time,Xilinx's TMRtool is comprehensively applied to implement TMR design of CCD driving timing.(3)Experimental verification.This thesis designs a software fault injection method based on scrubbing technology.Two SEU mitigation schemes are implemented on the hardware experimental platform.The experimental results show that the mitigation schemes are effective,and the scrubbing time is about 240 ms,the readback and scrubbing time in scheme 2 is about 480 ms.The FPGA in this article adopts the SelectMAP interface to perform configuration,scrubbing,and readback operation.The SEU mitigation schemes in this article can be easily transplanted if the FPGA devices are replaced by anti-radiation aerospace-grade devices.The design in this article can provide a technical support for related engineering.