1-GS/s, 14-bit digital-to-analog converter and track-and-hold amplifier

High-speed and high-resolution digital-to-analog converters (DACs) are one of the key components for wideband radio communication systems. However, the static performance parameters such as offset error, gain error, integral nonlinearity, differential nonlinearity, etc., are not directly applicable to these kinds of applications. For telecommunication applications, it is the dynamic performance that determines the quality of DACs. Among the most important dynamic performance parameters are spurious-free dynamic range (SFDR) and signal-to-noise-and-distortion ratio (SINAD). SFDR, perhaps the most often quoted DAC specification, defines the difference in decibels (dB) between the rms power of the fundamental and the largest spurious signal within a specified frequency band. SINAD is the most encompassing frequency-domain specification since it includes all of the noise and distortion that falls within the Nyquist frequency.; This thesis presents several novel approaches to improve the dynamic performance of a high-speed, high-resolution, digital-to-analog converter. In order to improve the resolution of a 14-bit DAC, a double-segmented decoder plus R-2R architecture will be introduced. DAC system modeling shows that the dynamic performance of the DAC is strongly dependent on the output impedance of DAC current sources. The gain-boosting technique is applied to increase this impedance. A novel switch driver is introduced to further improve dynamic performance by isolating digital switching noise from the analog output. Multiple-level emitter-coupled logic (MEL) is applied to the decoder logic due to its superior propagation time over emitter-coupled logic (ECL). Also, an emitter-degenerated current switch is applied to improve the settling time and resolution. The DAC circuit was designed using a 60-GHz fT InGaP/GaAs HBT technology. From circuit simulation, we find 0.31 least significant bit (LSB) differential nonlinearity, 0.35 LSB integral nonlinearity, and 0.75 ns settling time.; A 1-GS/s, 14-bit track-and-hold amplifier (THA) has been studied as the second half of this dissertation research. The THA is a key subcircuit in a data acquisition and conversion system. The input buffer of the THA employs an open-loop linearization technique to reduce distortion and increase bandwidth. The hold-mode feedthrough is reduced by the replica switch technique. The parasitic capacitance compensation technique is employed to further improve the signal bandwidth of the THA. Simulation results indicate that the parasitic capacitance compensation technique improves the bandwidth by approximately a factor of 5. The THA circuit was also designed using a 60-GHz fT InGaP/GaAs HBT technology. Simulation results are 83-dB SFDR at 100-MHz sampling frequency, 65-dB SFDR at 1-GHz sampling frequency, and 60-dB SFDR at 2-GHz sampling frequency under all Nyquist conditions.