Can Be Configured To The Research And Implementation Of The Wireless Transmitter System (gsm / Tdscdma / Wcdma), Low-power Dac And Filters

In the present market of wireless communication systems the demand of portable terminals able to satisfy the requirements of different standards is growing rapidly. The realization of single-chip wireless transceivers integrated in the most advanced scaled-down technologies is one of the most important issues. Therefore, reconfigurability is becoming a key point in the design of the baseband and RF architectures for wireless applications.Another important issue in the design of single-chip wireless transceivers is minimization of power consumption and die area. A proper choice of the architecture of the entire system is the key to optimize the two parameters. In addition, a progressive reduction of the supply voltages could strongly limit the power consumption. However, the low-voltage trend also increase the design difficulty of achieving large output dynamic range and high linearity performance, both of which are usually required in the blocks of transceivers. As a matter of fact, the implementation of high linearity analog blocks using a low supply voltage such as 1.2V can still be considered a challenge.The main purpose of this thesis is to realize a reconfigurable baseband analog block composed by a digital-to-analog converter (DAC) and a low-pass reconstruction filter (LPF) to be embedded in multi-standard (GSM/TDSCDMA/WCDMA) wireless transmitters with a standard 0.13-μm CMOS technology operated in a single 1.2-V supply voltage. Based on this purpose, a lot of work about theoretic research and circuit implementation is carried out.The main research contributions of this work include the following aspects:(1) The influence of random mismatch of the current sources on the integral nonlinearity (INL) of the DAC has been reinvestigated, and a new restriction of relative current-source matching for a given INL yield has been proposed, which is much less stringent than previous work and implies a much smaller chip area of DAC. (2) The effect of output impedance of current source on the integral nonlinearity and spurious free dynamic range of DAC has been modeled for both single-ended and differential output cases.