H.264 Video Encoder Based On FPGA

With the development of communications,electronics and computer technology, human racehas entered a multimedia era.Applications of multimedia are increasingly applied in people’s livesand enrich people’s lives,meanwhile,the technology of video coding is playing an crucial role inmultimedia applications.As digital video signals are huge and storage of devices and networkbandwidth is extremely limited,H.264 video coding standard came into being.H.264,which is thelatest video coding standard,has significant coding performance improvement over exitingstandards. However the high compression rate is based on sophisticated algorithms and thesecomplex algorithms put forward higher requirements for either software or hardware.Numerous mathematical operations in H.264 standard and sequence of software design makethe software can not meet real-time video signal, however the shortcoming could be overcome byFPGA.In this paper,I deeply study the main structure of H.264 encoding based on H.264 videocoding protocol and referring to the corresponding coding algorithm to meet parallel processingarchitecture,specially,the circuit consists of intra prediction,integer DCT transform, quantization,zigzag scanner and CAVLC entropy.In each module, I will supply each VLSI architecturedesign,RTL-level design synthesis and simulation picture.First of all,in this paper the H.264 video coding standard and its structure are described,which the core design features are though described.Secondly, the intra prediction,integer DCT,quantization,zigzag scanner and CAVLC entropy are exhaustively introduced based on existingalgorithms. Lastly, each circuit VLSI structure is presented.In this paper,full search mode is applied in intra prediction module and strive to minimizeresidual signal.the data path and control path hardware circuit are proposed,which consist of fivePE2 and seven PE3.All circuit output 16pexels per cycle;existing mature butterfly is applied inDCT transform,but the circuit is redesigned to minimize the latancy.Two-dimensional integerDCT transform can be accomplished after two one-dimensional DCT transform and transpose canbe available by RAM or on-chip registers;In order to meet the real-time encoding,a parallelprocessing of data quantization is designed based on look-up table.This circuit could process fourdata per clock and match well with integer DCT transform;Compared to the conventional designof entropy encoder,an improved hardware architecture CAVLC entropy which takes up fewerhardware resources is proposed.In the CAVLC pipeline and parallel approach are used tominimize the time of delay.