Research Of Parallel Realization In Sonar Array Signal Processing

The massive processing volume of large scale scientific computation and high speed real-time singnal processing should be realized by parallel processing technology instead of the conventional single-processing systems with limited processing capability. And with the fast development of acoustic signal processing theory, the new acoustic systems with high speed and huge data throughout have been proposed. At the same time the development of corresponding parallel arithmetics with great efficiency and accuracy is very important. The dissertation discusses the parallel realization of the key technologies in acoustic array singal processing based on the extensible high-speed parallel acoustic signal processing system with Quad_C64X broads. The detail of the research contents sums up as follows:Chapter 1 gives a comprehensive description about the significance of the research, the current status of acoustic array signal processing, and the key components of parallel teconology. The research orientation and structure of the dissertation are also introduced.Chapter 2 firstly explores the structure of extensible universal parallel sonar signal processing system based on static interconnection networks. Subsequently the data transforming logic between the parallel processing nodes is elaborated, and the general result of accelerated rate and efficiency of the above parallel system are analysed. Finally the parallel policy and the pipelining arrangement of the system are also gived.Chapter 3 introduces the parallel realizationg of tipical conventional beamfroming arithmetics. The parallel realization of conventional beamfoming based on DSP and FPGA are generalized, and the parallel performance of the above methord is analysed on the real system.Chapter 4 firstly elaborates the QR decomposing SMI arithmetic based on adaptive beamforming with LVCM rule. Subsequently according to the parallel character of Givens rotate in the course of QR decomposing, a parallel arithmetic with sub-task is proposed. Finally the Systolic realization of QRD SMI arithmetic and IQRD SMI arithmetic is explored, and the hardware structure of Systolic array on FPGA is gived.Chapter 5 explores the design and the realization of constant beamwidth beamforming. Firstly the frequency domain realization method of constant beamwidth beamforming is gived. Based on the realization method, the weighting vector design for discretional sensor condition is analysed. Subsequently a two filter structure constant beamwidth design method is proposed. In addition the constant beamwidth beamforming for nearfield spherical wave is elaborates. Finally the realization method of constant beamforming arithmetic on real parallel system is gived.The last chapter summarizes the main research conclusion of this dissertation, and the prospect of further research works is also projected.