Suitable For Multi-mode Wireless Communication System Reconfigurable Pipelined Adc Research And Design

As the digitizing interface advancing towards to the antenna in the modern wideband wireless receivers, the demand for high-resolution high-speed analog-to-digital converters (ADCs) is increasingly intensified. Reconfigurable and Software Defined Radio (SDR) architecture are recognized as two most promising candidates for seamless transition of mobile communication system from the current second generation (2G) to 3G and even beyond. Among the existing ADC architectures, pipeline architecture, in terms of power dissipation and area efficiency, is widely acknowledged as the best choice for high-resolution high-speed applications. However, to achieve a high resolution and a high conversion speed provided a low power supply, meanwhile reducing power dissipation for a pipelined ADC is actually a critical design challenge.This thesis focuses on the design and measurement of both high-resolution and high-speed ADCs, two prototype ADCs for the two application cases above are presented. One is a sub-sampling ADC designed for an impulse radio ultra-wide band (IR-UWB) receiver with its key performances verified by silicon as 1-bit 3GS/s, achieving 62.4mVpp sensitivity at 2.1 GHz input frequency and consumes only 22.5mA current under a single 1.2V power supply. This chip is fabricated in 0.13μm RF CMOS process. In order to alleviate the speed requirement for the comparators and digital blocks,16 time-interleaved channels are adopted at the cost of even stringenter design challenge on generation of channel-selection signals charactered by 1:16 duty cycle and 333ps pulse width. A ring oscillator with novel D-type flip-flops is presented to address the right problem. As well, a high-performance prescaler is proposed as a critical part of Mode-128 divider in a phase-locked loop to generate the global system clock.The other is an intermediate-frequency (IF) sampling bandpass reconfigurable pipelined ADC aimed for a multi-standard wireless receiver with conversion speed from 10MS/s to 100MS/s and resolution as high as 14-bit. A three-phase switched-capacitor MDAC architecture is used in order to speed up the settling procedure. Based on the various non-idealities, a systematic optimization platform is presented to facilitate the system design so as to obtain an optimal power solution. The reconfiguration function is mainly achieved by changing the biasing current for the Op-amp. Therefore, the optimization of the system and Op-amp is the two research stresses of this thesis. This thesis takes advantage of a highly matched MIM capacitor topology and a digital calibration algorithm. The target performance of the chip is 72dB SNR at 14-bit 100MS/s operating mode with a power consumption bellow 100mW under a single 1.2V power supply. This chip is now under fabrication with 0.13μm RF CMOS process.