Esd Protection For Mixed Analog-digital Integrated Circuits

During the manufacture and application of integrated circuits, the Electrostatic discharge (ESD) may cause ICs failure, decrease the reliability of ICs and increase the cost of ICs, so anti-static ability of ICs are required.In this thesis work, some CMOS on-chip ESD protections are investigated. It simply analyzes and compares resistances, diodes, MOS transistors, SCRs and bipolars when they are used as ESD protection methods. Then it uses MEDICI to analyze the snapback characters of GGNMOS structures and SCRs. For GGNMOS structures, it studies gate lengths, gate-to-drain contact spacing (GDCS), gate-to-source contact spacing (GSCS), gate voltages, substrate voltages, substrat concentrations and junction depths for the ESD reliability. For SCRs, it studies N-epi concentrations and the distances L between cathode and anode for the ESD reliability. On this basis, studies the whole chip ESD protecting structures, analyzes the ESD clamps between VDD and VSS/ground. For an ASIC, after taping out and test, proving the important of the ESD clamps between VDD and VSS/ground for the ESD reliability. On the other hand, with the improvement of the process such as LDD and Silicided Diffusion, new challenges appear in the ESD reliability. This thesis also introduces some new processes to overcome these challenges. Moreover, it refers the design rules of the layout and focuses the important of the layout for the ESD reliability. Last, as a further verification for the above analysis, this thesis designs ten different ESD protection structures for mixed-signal ICs using 2P4M CMOS process. Now, the taping out, the package and the testing are finished, the resuilts are consistent with the analysis in chapter 3, moreover, it can prove the importance of the whole chip ESD protection.To sum up, this thesis begins from the ESD models, analyzes the on-chip ESD protection methods with MEDICI. It verifies the analysising results after taping out and test to improve the ESD reliability of the mixed-signal ICs.