Research Of ESD Protection Design And Reliability Of ICs In Advanced Process

Electrostatic discharge (ESD) as a common natural phenomenon in life, takes a serious threat to the reliability of integrated circuits (ICs). In order to ensure the yield of the chips, on-chip ESD protection circuit has become an indispensable module in circuit design. With the continuous development of IC technology, the chips become smaller, faster and more deeply integrated. While the simple diode, gate-grounded NMOS (GGNMOS) and low-voltage-triggered silicon controlled rectifier (LVTSCR) devices in traditional ICs have been unable to fulfill the ESD protection task in advanced technology. There is an urgent demand to carrying out ESD protection design researches in advanced technology. To address the ESD reliability problems of nanometer IC, radio frequency (RF) IC and high-voltage power IC, comprehensive and in-depth researches had been conducted in this thesis. The main work and innovation include:1. Due to the fact that the trigger voltages of traditional ESD protection were too high to effectively protect the nanometer ICs, this thesis presented a novel substrate-current-triggered and substrate-resistance-modulated GGNMOS, an improved LVTSCR, and a boundary-MOS-triggered SCR structure. Based on the currently advanced65nm/55nm CMOS technology at home, firstly, this thesis studied the statistical distribution of transient gate-oxide breakdown voltages of the MOS transistors with different layout patterns, summarized the general laws of gate-oxide failures and the optimization methods, and drew up the ESD design window of the65/55nm CMOS process. Secondly, by theoretical analysis and calculation of traditional diode, GGNMOS and LVTSCR structures, we deduced the optimization methods to reduce the trigger voltages of traditional ESD devices, and proposed a novel substrate-current-triggered and substrate-resistance-modulated GGNMOS structure, an improved LVTSCR, and a boundary-MOS-triggered SCR structure. The trigger voltages of the proposed GGNMOS and SCR devices were successfully reduced to less than4V.2. In order to solve the problem that the parasitic capacitances of traditional ESD protection devices are to large to be used for ESD protection in65nm RF ICs, this thesis analyzed and compared the figure-of-merit of traditional ESD protection devices for RFIC through extracting the parasitic capacitances of the ESD devices. On this basis, a novel improved diode string structure had been proposed. By using the improved diode string and the improved LVTSCR as mentioned before, this thesis achieved successful implementation of ESD protection for a65nm CMOS3-10GHz ultra-wideband low-noise amplifier (UWB LNA). The deivce simulation and experimental results proved that both ESD protection strategies all achieved goals of low capacitance and low clamping voltage. The whole chip reached2.5kV HBM ESD level, while the S-parameter degradation of the ESD protected LNAs were less than15%.3. Based on the advanced0.35um5V/30V BCD process and0.5um5V/160V SOI technology, this thesis proposed whole ESD protection strategies for high voltage power IC. By means of theoretical analysis, device simulation and on-wafer measurement, the trigger voltage degradation of LDMOS, ESD characteristics of SOI LIGBT at different gate bias condition, and its trigger voltage walk-out effect had been researched. This thesis successfully completed the ESD protection design for plasma display panel (PDP)160V row driver IC product, which involved in one of the National Science and Technology Major Project (2009ZX01033-001). At last, this product had passed HBM2kV, MM200V and CDM500V ESD tests and met the requirements of this project.