For Satellite Navigation Applications, The Local Oscillator Chip Module Design

With the rapid development of IC(integrated circuits)fabrication processing and wireless communication technology, the implementation of a multi-standard, low-cost and fully integrated RF transceiver has become certainly the trend of development. The frequency synthesizer is a key building block in the RF transceiver. It is the determining factor of the overall performance of transceiver, and is also the biggest obstacle for its monolithic implementation. Due to theΣ-Δfractional-N frequency synthesizer completely overcomes the tradeoffs between loop bandwidth and channel spacing, and it can obtain a finer frequency resolution, lower phase noise and faster frequency switching, the more and more attentions have been put on it by the system designer recently.But PLLs design Proeess involves much theory and application base,Such as signal and system, integrated eleetronics, layout, semiconductor technology ,measurement etc. So , it's very necessary to deeply research the principle of Phase-locked System,capture the design and analysis method,set up IP library and afford ready design block for system.Firstly, by reviewing the developments of satellite navigation briefly and RF front-end circuits, this paper analysis the significance of integrated PLL in one chip. Then this paper analysis the basic theory of fractional PLL and the performance of fractional PLL, focus on phase noise and spurs effected by each module. Theses resolutions are applied in design followed.Through analyzing and researching on basic theory of fractional PLL, PFD, CP, MMD are designed based on satellite navigation application in this paper. Dead-zone is an impotent index of PFD. A PFD with low power and no dead-zone is presented by increasing feedback in loop. Different charge and discharge paths induce different pulse edges and value of charge current, and then some mismatch will appear. CP designed in this paper overcomes this question better. Because better tradeoff between high speed a-nd low power, phase-switching MMD is designed.Finally, according to TSMC 0.35μm SiGe BiCMOS model, the sub-circuits in the designed PLL are simulated and verified by the Cadence Spectre software. The simulation results show that when the power supply is 3.3V and the input reference frequency is 10MHz, PFD without dead-zone and the power is about 1mW; With charge and discharge current are both 250uA, the charge-discharge voltage range of CP is 0.15-3.25V, and the power is about 2mW; As input signal is sine wave and frequency of it is 2.55GHz, MMD's divide value from 128-255, power of it less than 14mW.