Applied To Short-range Wireless Communication Transmitter Research And Design

Based on the application background of SWRC(short range wirless communication),this thesis first introduces the product and market of SWRC device.The transmitter architectures which are appropriate for short range device and its performance,especially the direct modulation of PLL(Phase-Locked Loop) division factor,are analyzed.Also,the specifications for two transmitters are deduced from the European and Japan communication standards.Besides,the noise models of∑Δfractional-N PLL,especially the building blocks like PFD(Phase-Frequency Detector),CP(charge pump),VCO(Voltage-Controlled Oscillator),∑Δmodulator,loop filter and divider,are analyzed in detail.Furthermore,the loop filter parameters for 3^rd and 4^th order PLL,and settling time of PLL is given.With the introduction of capacitor ratio b and pole position ratio k,the system performance of 4^th order PLL becomes intuitive.A new design procedure is summarized,which can b easily adopted for different applications.The first chip presented is a∑Δfractional-N frequency synthesizer for 434/868 MHz FSK/OOK transmitter.Direct FSK modulation is realized by switching between two different division factors,while OOK modulation is implemented with a switch to control the pre-power amplifier.Current controllable Voltage-controlled Oscillator(VCO) and on-chip differential-to-single converter are exploited to reduce the cost and power of the transmitter IC. The design of divide-by-two circuit(DTC) is also analyzed.The measurement results show that the phase noise is -75dBc/Hz,-104dBc/Hz,and -131dBc/Hz at 10-kHz,100-kHz,and 3-MHz offset with carrier centered at 868 MHz, respectively.The VCO presents a phase noise of-104dBc/Hz@100kHz offset. The measured adjacent channel power ratio(ACPR) for 100-kHz channel is less than -50dBc.The 2-mm² transmitter is fabricated with 0.35-μm RF CMOS process.The frequency synthesizer consumes 12.5mA from a 2.5V voltage supply.Another 433/315 MHz OOK direct digital modulation transmitter is implemented with 0.25-μm RF CMOS process.Different from the previous chip, PMOS current source is used to ensure that the VCO works in current limited region,which provides better noise and power performance.AFC(Adaptive Frequency Calibration) block is added to aid the fast-lock of PLL.Moreover,a pre-power amplifier with 3-dB step gain is presented.The measurement results show that the maximum output power of the transmitter at 315MHz is 7dBm with a 2.5V supply.And the current consumption of the transmitter with PLL under transmission mode is 25mA.The lock time is 12.5μs and the phase noise of the PLL is-132dBc/Hz@1MHz offset.