Hybrid Integrated Circuits Design For Testability

Progress in very deep submicron semiconductor technology enables the integration of a highly complex system on one single chip, it is so called System-on-Chip(SOC). As integration complexity increases, there exist many new difficulties in testing embedded analog cores in mixed-signal SOC.The application of Built-in-self-test(BIST)can reduce the SOC test and verification time, and improve the fault coverage. Therefore, the BIST technique is an important approach to efficiently test analog blocks of mixed-signal SOC. In this paper, mixed-signal circuit testing theories and methods have been studied and designed a ADC as an example to validate test results. To sum up, the main job has the following five areas.ⅠDFT of mix-signal circuitsIn order to reduce costs and improve fault coverage, cores must be design-for-test. To this end, this paper can be used to improve circuit testability measures.ⅡWith the protocol IEEE1149.4 test circuit structure and function.Based on IEEE1149.4 mixed-signal design for testability. Designed the TAP, the digital scanning units, Analog scanning unit, analog switchs and the register module.Ⅲ10-bit SAR ADC designDesigned for test and the test circuit must be synchronized, in mixed-signal, the most typical is the ADC. This paper designed a 10-bit SAR ADC, the product definition from the beginning to the end of the layout generation, to do in this article are discussed in detail.ⅣADC design for testabilityIn mixed-signal test, there is a lot of test points, the most common is testing each pin connected to the kernel case. Therefore, this paper place a scan cell at ADC each pin to test analog and digital signals.ⅤTechnology and layout verificationThis design uses CSMC domestic manufacturers corresponding standard CMOS technology process model, using Spectre of various sub-circuit modules of the simulation verification, using Calibre of various sub-modules layout of the DRC and LVS verification ,to ensure that its power and at different temperatures to achieve the design requirements of various indicators. Circuit will eventually flow using standard CMOS process, a total vertical PNP, PMOS, NMOS, resistors and capacitors five device structure.