Design For DSP Embedded Debug System Based On IEEE1149.1

With the development of integrated circuit design and manufacturing process, Digital Signal Processor has become more high-performance and more complexity.In order to ensure the yield of chips and improve the observability and controllability of the internal signals, how to improve the testability of the chip has become a difficult research problem.At the same time, The development of the software applications also become more difficult. Design on-chip-debug architecture for the DSP will provide effective support for complex applications.In this paper, with the study of DSP architecture, it proposed an on-chip-debug architecture based on the extended IEEE1149.1 protocol (JTAG).The on-chip debug system control the chip through the JTAG interface.It control the state of the core pipeline, and could observe the chip state with the help of the scan-chain-register.It also could read and write the core registers under the control of the debug unit.The design successful implement basic debug control functions including hardware and software breakpoints,single-step debug and etc.The Debug system based on JTAG interface is composed of TAP controller, instruction register, data registers, boundary scan chain structure, on-chip debug modules, and so on.It implement board-level testing and on-chip-debug, and communicate with the host computer through the common JTAG interface which do not need to add new pins.RTL-level codeing for on-chip-debug unit was finished.And complete post simulation vectors were developed to ensure the correctness of the design.