System-level Chip Testability Research And Practice

With the development of IC design and manufacture technology, SOC (System on Chip) becomes more and more popular. But since the SOC product includes some different modules, its testing job became more and more complex, and the test time becomes longer, the cost of testing becomes higher. At the other hand, the time to develop a product should be shorter with the development of Co-design. To resolve these problems, the system designer should take the testing into account when they design a system and circuitry.That means the standard of evaluating a system or circuitry includes not only the system capability, the amount of component, but also the testability, the convenience of test. So we call it design for testability (DFT) .This paper researched into the design for testability of IC testing. And the contents of this paper are listed as follows:Firstly, this paper talk about the significance and way of IC testing, the testing challenge in SOC projects. And then, introduce DFT (design for testability); analyze its merits and shortcoming.Then this paper summarizes the design for testability of HDVP2X. And pay more attention to introduce the method of design for testability which was used in HDVP2X design for Scan, analyzes its logic of control part.Finally, this paper takes a design for testability of embedded SRAM on the base of experience and some articles. In this part, the paper firstly introduces the Built-in-Self-test (BIST), and then introduces the types of malfunction, and test algorithm.Boundary Scan Technology (JTAG) was attempted in HDVP2X project. It's not only helpful for system level testing, but also a good method in IC testing. Internal SCAN and BIST can be easy accessed and controlled via JTAG.