Design And Implementation Of GHz Level Digital Module Test Architecture

With the rapid development of integrated circuits design and technology scaling, many parasitic effects become more severe, which lead to unconsistency between the test results of real chip and the analysis before taping out. Therefore, circuits must be verified through taping-out in order to ensure the correctness of chip design. This thesis investigates the test architecture of digital module in GHz level. GHz level digital module has a lot of input-output ports. The common used direct test method needs many expensive and high speed I/O pins which will occupy a majority of chip area and the packaging cost of high frequency chip is very high. So this thesis tries to design a reusable taping-out test architecture with little pins and low cost which can also surport the debug and test of clock frequency ranging in GHz level.A solution of GHz level digital module taping-out test against the problems metioned above is presented in this thesis, and a full-custom CAM taping-out test in 65nm CMOS process is also implemented. The main contribution and innovative points are as follows:1. The strategy of combining the JTAG protocol and scan chain technology is applied. The strategy can not only reduce the number of pins effectively, but also realize the fully controllability and observability.2. The design method of clock alterable frequency and clock frequency switching is proposed, which can solve the problem of requiring multi-frequency points in taping-out performance test structure and high cost in functional testing. The range of reconfigurable performance points of test frequency is between 10MHz and 2.4GHz which can meet the demands of performance test.3. Based on 65nm CMOS process and using semi-custom design flow, a GHz level digital module taping-out test architecture has been implemented. The taping-out test implementation of a full-custom design of CAM has been completed. Its layout area is 0.385 mm2. In contrast with the similar method, this design saves much more area. Besides, it doesn't use high speed I/O interfaces to output response which can reduce cost greatly.