Design And Research Of JTAG

Boundary-scan technique is a testing method of IEEE. Realization of JTAG reduces the complexity of testing, and increases time to market, thus it is suitable for testing of VLSI. Meanwhile, due to stronger function with smaller volume, mainly used in research on IC design and verification, but to realise bounsary-scan will requires7% extra area, increase the number of lines, and decrease the operating speed. All these problems are to be solved.According to research on JTAG standard and technology conception, the JTAG application architecture in SoC device is analyzed, a simplyfied measure is proposed. Based on this, embeded JTAG IP core which is applicable in chip testing is designed. The JTAG IP core has the following features: simple structure, mature in technique, widely supportive, variable testing method design, high precision error location, and it is widely used in SoC design.Through academic research, detailed method of JTAG realization is presented, and for the first time, how to select the number and length of scan chain and testing dissipation are analyzed. The paper is closely attached to IEEE1149.1 standard, and the novel idea lies in the fact that after analysis on JTAG instruction and RTL level modeling and simulation of JTAG, the fundamental part in JTAG testing follows the specification, boundary-scan testing is applied to actual circuits, and finally the theory of boundary-scan is verified. Through simulation and verification, the reliability and feasibility are satisfactory, and it is of good value.