Research On The Key Circuit Of Reliable Low Power EEPROM Memory In RFID

With the rapid development of China’s strategic emerging industries,the Internet of Things(Io T)plays an important role in accelerating economic development and social livelihood.Due to the important role of RFID(Radio Frequency Identification)in Io T technology,RFID technology has also been deeply studied in this background.In the RFID tag chip,EEPROM(Electrically Erasable Programmable Read Only Memory)is used for storing and rewriting data,and the operation of the RFID tag is equivalent to the operation of the EEPROM memory.Therefore,the performance of RFID tags and EEPROM memory performance is closely related.This paper analyzes the key circuits of EEPROM memory and improves the overall performance of RFID tags by optimizing the design of partial circuits.Firstly,the theory of EEPROM memory cells is elaborated in this paper,and the working principle of memory cells under three operating modes is analyzed in combined the equivalent capacitance model.The system principle of the EEPROM memory is analyzed and explained,and the overall structure of the EEPROM memory is analyzed from the perspective of the circuit function so as to understand the function of the chip.Secondly,the three sub-modules of high voltage circuits: charge pump,clock generation circuit and voltage stabilization circuit are studied and analyzed.In order to reduce the influence of reverse leakage current on input stage,and avoid the output voltage fluctuates with the clock voltage,the input stage and output stage structure of the full PMOS substrate floating charge pump are improved.The clock generation circuit generates a four-phase clock-driven charge pump,and the voltage of two-phase clock among them is doubled,which can effectively suppresse the reverse leakage current and improve the boosting efficiency of the charge pump.The voltage regulator circuit adopts the switch capacitor circuit to feedback the clock generation circuit,the charge pump climbing time is elongated,thus the impact of peak current is reduced during boosting.The SMIC 0.18μm EEPROM process is used to verify the high voltage generation circuit.As the clock voltage increases,the boosting speed of the charge pump is also improved to a certain extent.Finally,the charge pump,clock generation circuit and voltage stabilization circuit are combined to simulate.The simulation results show that the high voltage generating circuit designed in this paper can achieve a high voltage output of 16.3 V at around 315 ?s,which can meet the requirements of the chip.Finally,the sense amplifier and column decoding path of the readout circuit are analyzed and designed.Among them,the sense amplifier adopts the hysteresis comparator instead of the normal comparator,and the column decoding path uses the three-stage transmission gate to realize address selection and serial readout.Sense amplifier and decoder are verified by simulation.Through the simulations of "0_cell" and "1_cell",it is proved that the sense amplifier can accurately distinguish the stored information "0" and "1",which can achieve data reading.Since the 2-4 decoder is the main component of the column decoding path,the 2-4 decoder is also simulated to prove that the column decoding path can correctly implement the address selection.