.6 G Ultra-wideband Source-coupled Logic Divider

The growing popularity of Internet demands high data rate wireless local area network. Using the unlicensed national information infrastructure (U-NII) band, wireless local area network systems can provide data rates up to several tens of megabits per second.The main purpose of this paper is to realize the frequency synthesizer for the 6GHz wireless local area network transceiver system. The frequency synthesizer is being used to produce the accurate local oscillator signal and to produce different centre frequency according to the channel plan.In chapter 2, the different structures of RF transceiver are discussed. It is essential to the whole performance of the radio system to choose the proper structure.The main structure of the divider is a digital block, so we analyze the digital block definition and the second effects we should consider in sub-micron process.In chapter 4, we elaborate the different structures of the digital divider, and we decided to adopt the integer divider after the overall consideration.The chapter 5 is the focus of this paper. We analyze the design method of the source coupled logic divider, which include the design of resister, current source, SCL D-latch block, and input and output buffer. Then we show the functional simulation results of the divider.In the next chapter, we touch on the design of the layout, with the consideration of some effects such as antenna, WPE and STI effect we should take care. Then we extract the parasitic resistance and capacitance as we should use them to perform the timing simulation. Finally we optimize our circuit according to timing simulation results.The measurement of timing simulation is shown at last. The SCL divider works at 6. 336GHz and the reference spurs achieves -101dBc.