Chips Design For Frequency Synthesizer Based On Phase-Locked Loop

The medium of wireless communication chose electromagnetic waves instead of traditional cable, and had been pursuing more portability. Due to the advantage of dimension, the integrated circuits become the most suitable carrier. This thesis discusses around the PLL-based frequency synthesizer, which is the key component in integrated RF transceiver. Starting from the theory, this thesis comprehensively introduces the whole process including calculation of the loop parameter, design of module circuits, planning of layout, the tapepout and chip testing. Solutions in choice of the VCO’s tail current sources, realization of the low supply voltage VCO and design of the CML divider have been proposed. This thesis has the following achievements:The working principle, the frequency characteristics and the noise characteristics of PLL are presented. This thesis discusses the source and mechanism of the main nonlinear effects in the loop, followed by the corresponding solutions.Several techniques to improve the phase noise performance are summarized. This thesis compares the effects of the presence or absence of the tail current source in VCOs. Based on the comparison, an improved switched biasing topology has been proposed in QVCO design. This topology forms a "pseudo-Z" state during the operation, decreasing the loss of tank caused by the cross-coupled Mosfets in linear region. Meanwhile, the advantages of the conventional switched biasing technique have been retained to suppress the flicker noise. The QVCO has been frabricated in0.18μm CMOS technology, working at4.56GHz under1V supply voltage. A FOM of186.5dBc/Hz and a tuning range of17.3%are achieved.This thesis discusses the necessity and the problem in low supply voltage VCO design. An inductive biasing network is proposed. The amplitude at the gate node of cross coupled Mosfets could be3times larger than that at the output node in the VCO. A detailed theoretical analysis proves that the multiple relationship will reduce the channel noise contribution from the Mosfets, so as to improve the phase noise performance of the VCO. Additionally, this network will bring some other improvements in the oscillation frequency and Q factor of the tank. Cooperating with the adaptive body biasing technique, the proposed VCO oscillates at4.56GHz under 0.3V supply voltage and achieves a FOM of192.5dBc/Hz. Measurement results in0.13μm CMOS technology verify the validity of the inductive biasing technique.This thesis introduces the classification and operating principle of the loop divider, prescaler and/2divider. In terms of the difficulty in the design of working frequency and range, the CML topology with inductive peaking technique has been analyzed and realized in0.18μm CMOS technology. Measurement results show that this CML divider consumes3.6mW power consumption and achieves a range of2-9GHz. The test results of two prescalers are also given.According to the requirements of IR_UWB system, the PLL parameters are calculated in detail. A charge pump with feedback topology is proposed, enhancing66%of the dynamic range compared to that of the traditional structure. Implementations of PS counter and Sigma Delta Modulator are also introduced. This thesis realizes two faction-N PLLs for6-9GHz IR_UWB system in0.18μm and0.13μm CMOS process. Measurement results show that the phase noise of the two PLLs are-68.6dBc/Hz@10KHz、-111.3dBc/Hz@1MHz and-80dBc/Hz@10KHz.-111.8dBc/Hz@1MHz, respectively, meeting the system requirements.