Static Timing Analysis And Optimization Of Digital Chip Based On 28nm Process

With the rapid development of integrated circuit industry, the size of chip design is growing, and the clock frequency of the chip is increasing. Timing analysis becomes a complex and important task in the design check of the chip. The data in circuit can be latched and transmitted correctly only when the chip meets all timing requirements, which ensures that the chip operates properly and achieves the desired performance. With the increasing frequency and more complex function of the chip design, timing analysis is faced with challenges. The timing performance and function of the chip depends on whether the timing violations which occurred in timing analysis can be fixed or not. Therefore, the methods to fix the timing violation reasonably and correctly become a key aspect of the design of chip timing.Based on a 28 nm process digital mobile baseband chip designed by the author's company, the thesis studies static timing analysis about digital chip. With the extracted netlist and spef files after the place and route step in physical implementation of the chip, the thesis uses Primetime tool to perform the MCMM(multi-corner multi-mode) static timing analysis and fixes timing violations in analysis results by ECO. This thesis considers the effects of signal integrity in timing analysis, and improves the accuracy of timing analysis in the means of advanced on-chip variation proposed in 28 nm process. Based on the theory of AOCV in 28 nm process, the thesis proposes a novel timing path delay calculation method. The thesis studies and summarizes the optimization methods of the delay unit which are adapted in ECO. This thesis studies the timing violations in design of the chip, including setup time violation, hold time violation, recovery violation and removal violation, the maximum conversion time violation and RC-011 problem, and fixes those timing violations by optimizing the delay of the standard cells in timing paths, and achieves the timing requirements of the chip and optimizes overall performance of the chip by taking into consideration of the physical and power aspect.Based on the AOCV theory in 28 nm process, a new method to calculate the delay of timing path which is proposed in this thesis, compared with traditional timing analysis method, can reduce the calculation of common path delay in timing path, which has certain theoretical and reference significance for optimization of timing in IC design and development of static timing analysis tool. The methods of fixing timing violation which this thesis proposes are practical and have been used for timing optimization in many projects and have a certain practical significance.