Design, Fpga-based H.264 Video Encoder

Along with the development of the coding technical.The standard of the video frequency got the successful application in lots of realms.Such as video conferencing (h.263),DVD(MPEG-2),the set-top box(MPEG-2) etc.And in the future, the network bandwidth promotes continuously and efficiently the technical development of the video frequency compression make people turn the foucus on the business base on the transmission such as the network numerical television(IPTV), flow medium...etc. The increase in bandwidth for streaming media paved the way for the development,and the efficiently standard of the video frequency compresses would be the key of the medium technique development. H.264/AVC is the ITU-T and the ISO common development of the next generation of video compression standards. New standards adopted a new video compression technologies, such as multi-mode interframe prediction, 1 / 4 pixel accuracy of forecasts, integer DCT, variable block size motion compensation, based on the context of binary arithmetic coding (CABAC), based on the context of variable length coding (CAVLC) and so on, the introduction of these technologies has greatly enhanced the efficiency of video compression, broadband network is more conducive to the realization of the business base on the transmission such as the network numerical television(IPTV), flow medium...etc.This paper mainly based video conferencing applications need to optimize the code JM8.6, the aim is to achieve Baseline CIF encoder。Methods used in the design is top-down design method, the first optimize C code and algorithms of H.264 encoder, and test the results。The results showed that the image quality has not decreased significantly circumstances, H.264 encoder encode CIF format 15fps above,it meets the real-time requirements of video conferencing applications. And then use C model as a reference and design the part of the H.264 encoder function module circuit using Verilog HDL Implementation of these modules, and use Quartus II to synthesize, simulate and verify . Main completed the Zig-zag scanning and CAVLC module design, detailed description of the working principle and module process, and then teams of the simulation test results with the corresponding part of the C model consistent results proved the correctness of the design.