| The H.264/AVC (Advanced Video Coding) video compression standard, jointly developed by ITU-T and ISO/IEC, provides a high performance over other video compression standards. However, the high performance comes at significantly increasing the computation complexity. Extraordinarily, the run-time of H.264/AVC coding is occupied above 90% by inter Motion Estimation (ME) which include Integer Motion Estimation (IME) and Fractional Motion Estimation (FME) in order to implement Variable Block Sizes Motion Estimation (VBSME), multiple reference frames inter Motion Compensation (MC) and Rate Distortion Optimize (RDO). Therefore, hardware architecture and VLSI design of ME is very important for H.264/AVC encoder.In the H.264/AVC encoder, IME module is responsible for motion search of multiple reference frames and big search range. Several fast algorithms and hardware architecture are proposed for IME to meet real-time requirement. But for FME which is responsible for 1/2 pixel and 1/4 pixel motion estimation with RDO according to results of IME. Moreover, FME is responsible for Lagrangian mode decision and MC of picture Macro Block (MB) based on 1/4 pixel FME results of 41×n sub-blocks with multiple reference frames. Obviously, FME is not only computation complexity but also requires a very high hardware implement cost.Therefore, in this paper, aims at to implement inter encoding of H.264/AVC and to meet the need of encoder system, a pipelined hardware architecture of FME module and VLSI design architecture of all sub-modules are proposed. By analysis of FME, the module is carefully partitioned into some sub-module. Moreover, based on the design theory of balance of area and speed, the algorithm of FME is simplified and verilog HDL code of each sub-module are finished. Finally, these VLSI designs had been successfully implemented on Field Programmable Gate Array (FPGA) development board(Altera DE-2,Cyclone? II EP2C35F672C6 FPGA). |
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