Based On Power Consumption And Linearity Optimization Pipeline Adc System Modeling

A top-to-down model is build based on power and non-linearity of pipeline ADC, and which is done by analysis the working principle at the same time combining the given technics of SMIC .18μm . Methods to assign core specifications is bring forward when optimizing power of the system and considering linearity. Linearity model is built and optimized, followed by conclusions of to which degree index is affected by errors.A expression of system power is given ,combining with errors ,two main factors that affect power is deduce ,which are stage resolution distribution and value of capacitor. Circuit parameters that confine stage resolution and capacitor is analyzed. For the first stage, which have the most strict demand ,as the increasing of the stage resolution ,the requirement for capacitor is decreasing .GBW for MDAC amplifier is getting higher .Open-loop gain of MDAC amplifier mains the same ,do not change with stage resolution .Capacitor is defined by stage resolution and noise .Later stage resolution not bigger than former ones can release the requirement of capacitor of later stages , and smaller capacitor can be used and power is decreased.The power model is built and simulation of 12 Bit 100 Msps pipeline ADC is carried out . Simulation result suggest that ,for employing MDAC amplifier sharing technique ,when current of single comparator is lower than 186μA, (3.5+1.5×7+2)have the lowest power ,when current bigger than 723μA, (1.5×10+2)have the lowest power ,when current is between the above two , (2.5+1.5×7+3)is the lowest power structure .For employing one stage one amplifier technique ,when current of a single comparator is lower than 24.55μA, (4.5+1.5×6+2) have the lowest power, when current is bigger than 470μA, (2.5+1.5×8+2)have the lowest power, when current is between the above two, (3.5+1.5×7+2)is the lowest power structure.A speed model is built to instruct the choosing of settling of MDAC amplifier .The speed model of 12 bit 100 Msps pipeline ADC require for SR is faster than 800V/μs and GBW is more than 1.18GHZ for a first stage of 3.5bit and 648MHZ for a first stage of 2.5 bit. The influence of errors on system metrics is analyzed based on the selected structure, simulation and optimization is followed .Six sort of errors, which are noise from sampling capacitor, amplifier and voltage reference, limited open gain, capacitor mismatch, time jitter and voltage reference offset. Simulation result proves that the model is correct .Among these errors, time jitter and capacitor mismatch effect system metrics heavily. Capacitor mismatch have a great restrict on SFDR and secondly on INL .Time jitter have the opposite restrict on the two index. After adding all these errors together, the performance is better than adding them alone.