Pipeline, The Adc Behavior Modeling And Simulation

Pipeline ADC who has the benefits of high speed, high resolution and low power dissipation has been widely used as the markets of wireless communication, mobile multimedia and handheld terminal growth rapidly in recent years. So it is very important to speed up the pace of researching and designing the Pipeline ADC. The way of building the behavioral model and system optimization has been obtained to accelerate the speed of Pipeline ADC design in the system-level in this thesis.The method of building the behavioral model has been found through the analysis of sample and hold circuit, Sub-ADC, MDAC and error correction circuit. A second order mathematic model of the circuit is been built by mainly considered the settling error of the operational amplifier. Then the model is been built through this mathematic model by using SIMULINK. We build the model of Sub-ADC and error correction circuit by adding their ideal model with main error source. Other error source such as switch on-resistance, clock jitter, main noise source and capacitor mismatch and so on, are also been considered and modeled.The power of a Pipeline ADC who has the resolution of 12 bit and the sampling rate of 100MHz has been optimized based on the relationship between power dissipation and noise, at the same time combining the given techniques of SMIC 0.18μm. System has the lowest power dissipation when the structure of the system is (3.5+1.5×7+2) under the limit that the SNR of the system only drop 3dB by the affect of noise. The minimum sampling capacitor of the front-end stage is 1.43pF and the sampling capacitor of the back-end stage are (0.62pF+0.25pF+0.125pF+0.1pF×5) respectively when the full scale is 2V. After the structure of the system been confirmed, the design parameters of the operational amplifier which is the key component of Pipeline ADC is been optimized by combing the requirement precision of the output of each stage. The results show that the requirement of sample and hold circuit and the first stage MDAC who has the effective stage resolution of 3.5 is strict. The performance of them will affect the whole system and the requirement of the back-end will be relaxed. At last, a circuit has been designed for verifying the behavioral model. Simulation results show that there is only little difference between them, so the model can reflect the work of the circuit very well and it is more efficient. It is found that the SNR is 70.94dB and the SFDR is 82.88dB, ENOB is 11.49 bit, DNL is only 0.33LSB by the system level simulation when the temperature is 398K. These simulation results show that the performance of the system can meet the design requirement when we choose the design parameters as the optimized design parameters.We can quickly determine the system architecture and related design parameters by using this model and optimization method which have very important significance to speed up the design of Pipeline ADC.