Broadband Digital Channelized Receiver Fpga Technology

The main characteristic of electronic warfare is that it has wide frequency band, a great deal of signal types, moreover, the work pattern is non-cooperative. So we must study and develop a kind of receiver which includes wideband frequency coverage, high sensitivity and dynamic range, high probability of interception and full or near real-time operation.The digital channelized receiver based on poly-phase filters is an appropriate solution. In this thesis, design and implementation of a broadband digital channelized receiver are studied systematically. The main contents of the thesis are as follows:1. The advantages of digital channelized receiver and the trends of its development are discussed based on signal characteristics.2. The conventional theory of digital receiver, i.e., multirate signal processing, is introduced. Based on theoretical study mentioned above, the hardware-efficient digital channelized architecture with poly-phase filter banks is deduced and established. The simulation results show that the architecture is correct and hardware realizable.3. According to the project's requirements, technological difficult issues are analyzed, and an implementation structure, based on high speed A/D and FPGA devices, is presented in this thesis. Meanwhile the feasibility and block diagrams of system are completed.4. All functional modules of digital channelized receiver, including pulse detection, FIFO configuration, operation, output control and synchronization module on FPGA devices, are implemented. According to the characteristic of the interception data, the optimized implementation algorithms of poly-phase filter banks and IDFT can reduce the hardware resource demands and improve systematic operation speed.5. Experimental results of the presented digital channelized receiver verify its validity.