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Multi-parameter Radar Signal Measurement And FPGA Realizing Technology Based On Ploy-phase Filter Banks

Posted on:2012-06-07Degree:MasterType:Thesis
Country:ChinaCandidate:H F ChenFull Text:PDF
GTID:2178330332987573Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
Along with the development of digital signal processing theory and microelectronics, the digital channelized receiver had a further progress. The emergence of FPGA provides hardware platform for the development of digital receiver. This paper combines the reducing speed filtering algorithm and the FPGA design based on modern DSP technology. The digital channelized receiver is studied in it.Firstly, this paper simply introduces software radio in the three stages of development, and then correspond them to the three stages of digital receivers. The main research content includes the following several respects:(1) This paper introduces the basic theory of poly-phase filter banks based on FFT. It contains base-band sampling theorem, band-pass sampling theorem, multi-rate signal processing base, window function design method steps, ploy-phase filtering theory and the ploy-phase filter banks based on the Discrete Fourier Transform.(2) To be measured multi-parameter radar signal and the research of channelized processing based on multi-phase filter banks is given. It includes fast frequency measurement methods and implementation complexity base on the one stage of ploy-phase filter banks. The two stages of ploy-phase filter banks model are given. The simulation method and result of taking signal envelope in view of orthogonal double channel is presented. Overlapping signals of the signal envelope separation problem is solved by using poly-phase filter banks. Then ploy-phase filters banks+ FFT is used to achieve a high accuracy of test.(3) At last, two modern methods of DSP technology are given. The one, Modelsim is used to finish the former timing simulation, the comprehensive and post-layout simulation is realized in Quartus. The other is adopted the Simulink in Matlab to finish the former timing simulation, the comprehensive and post-layout simulation is realized in Quartus.
Keywords/Search Tags:Digital channelized receiver, Multi-rate digital signal processing, Parallel FFT, Ploy-phase filter banks, FPGA, FIR filters
PDF Full Text Request
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