Research On Multi-channel Digital Channelized Receivertechnology

Electronic warfare, which is an important part of the modern information war, usually can change the war process even the victory. War electromagnetic signal pulse is very dense due to being used a lot of on the modern electronic equipment whose electromagnetic signals are in various forms. Digital channelized receiver, which has a wide instantaneous bandwidth and can intercept simultaneous signals, is suitable for the modern electronic battlefield environment. So it is significant to research digital channelized receiver.The principle of digital channelized receiver is studied and the digital channelized receiver is realized in FPGA. According to the requirement, two channels of digital receivers need to be achieved in a single FPGA chip, so a highly efficient structure based on poly-phase filter and IDFT is chosen. The structure is deduced and realized, which includes data extraction block, poly-phase filter block, IDFT block, PDW generate block, PDW transmit block and PDW receive block. Simulation for each block is carried out to verify the correctness of the algorithm, then each block is designed in detail and debugged in the FPGA.In order to save multipliers in the FPGA and meet the requirements of high speed computing, the poly-phase filter is achieved using a parallel distributed algorithm. A parallel IFFT module is designed which can reduce resource consumption and meanwhile improve the computation efficiency, due to the FFT IP core is serial data input which can not meet the requirements of the system. A method to suppress the rabbit ear effect is proposed, which uses a state machine to check the pulse wi dth and can accurately measure pulse width.Finally, the design of digital channelized receiver is tested on the hardware platform, the results show that the system works properly and stably. The design can meet the requirements.