Research On Digital Warning Receiver

This paper presents an efficient architecture of digital channelized receiver based on IDFT poly-phase filter-bank. Its basic principle is to realize channelization efficiently by using poly-phase filterbank with decimatior and IDFT, output the base-band signals and give an accurate PDW output at a lower speed. In this way, it has high probability of interception and broadband instantaneous frequency coverage.First of all, one of the efficient architecture of digital channelized receiver is built in comparison with the basic architecture. The simulation results by Matlab indicate that it is a highly efficient and accurate architecture. Meanwhile, it simplifies the design of the latter parameter encoder.Secondly, several kinds of instantaneous frequency measurement methods are discussed. Then one simple method based on amplitude comparison and phase difference is proposed. The phase difference of the signals in each channel is properly designed by making an optimum selection of undersampling factor F to make a lineal response within 60dB bandwidth of every filter. It solves the problems that receivers couldn't response properly to the signals in adjacent channels.Finally, the implementation with FPGA based on the efficient architecture is proposed. Its main components are mainly described, including the unit of phase unwrapping and phase difference, the unit of PDW. The results from ChipScope suggest that this hardware scheme is simple to realize and covers all the design requirements.The scheme metioned in the dissertation has a bright future in the electronic warfare application.