Integration Of Fpga-based Real-time Image Processing System Of Logic Design

With the development of multimedia technology, digital image processing has become the core and foundation of application system. Image processing as an important modern technology has already been widely used in the fields such as military command, panoramic image exhibit, track radar, TV-conference and navigation. As a result, the implementation technique of image real-time processing for high-resolution and high refresh rates not only has widely application foreground, but also has far-reaching meanings to the related fields.The panoramic image system can only be demonstrated well at a special curved plane screen, because of its large screen size. The image should be corrected by geometric calibration and edge-blending before projection in order to display image on the curved plane screen correctly. However, Field Program Gate Array (FPGA) is the ideal hardware choice for real-time image processing. FPGA-based image processing technology is a worldwide concerned field.The main task of this project is to design an FPGA-based hardware system which can process high-resolution and high refresh rates (1024 * 768 @ 60 Hz) video images timely.This thesis presents the system scheme and functional modular division of FPGA-based wide field of panoramic image real-time processing system by dividing the image processing system into three major design parts: software and algorithms design, hardware design and FPGA logic design. This paper is mainly responsible for logical design of FPGA. Around logical design of FPGA, this paper first introduces the key technology for FPGA system design, and the principles of logical design by using of Verilog Hardware Description Language.This thesis emphasizes on the detail design of internal FPGA modules. Arbitration and control module is the main part of the top module used to implement the state machine and system timing control. Parameter table module is the SDRAM memory controller interface for reading parameter information when image processing. Image processing module which is the core of the whole system archives image data computing of multiplying and accumulating high-speedily by calling FPGA embedded XtremeDSP modules. Finally, the author put forwarded and realized a new-fashioned I2C bus interface which is based on the PicoBlaze soft IP core to configure FPGA's external chip.By synthesizing and simulating Verilog HDL code on register transfer level, the result shows that the designed system can be applicated in the field of the panoramic image system to complete real-time processing of high-resolution and high refresh rates image.