Design Of Image Acquisition And Processing System Based On FPGA

Image processing technology is inextricably linked to computer technology and microelectronics technology. There are diverse hardware platform which can be chosen to implement the image processing, and the algorithms of the image processing are being constantly improved. With high speed, parallel processing, flexible features, FPGA has drawn more and more attention in image processing field which has a large amount of data to be processed. The EP2C35F484C8chip of Cyclone II family of Altera’s FPGA is a kernel device in this paper. The OV7670camera module, the SDRAM module, the median filter, the edge detection module and the VGA display module are implemented in Verilog HDL on the tool of Quartus Ⅱ9.1.The system uses OV7670camera to capture the real time image data, and stores the RGB565format data to SDRAM. The SDRAM controller dominates the SDRAM initialization, read and write, refresh and other operations. The system get the image data out from the SDRAM, and use fast median filtering algorithm to process the image data. Then the edge detection module extracts the edge information from the image data. Both the median filter and the edge detection module use the macro module provided by Quartus Ⅱ9.1. After being processed, the image data would be converted to analog signal by chip ADV7123for displaying on the VGA monitor.The system uses the ping-pong operation to store and read image data, which accelerates the speed of storing and reading image data. The parallel processing methods are used in the median filter and edge detection module to improve the image processing speed.The tool of Quartus Ⅱ9.1completes the mission of design, simulation and verification. The whole system is validated by the hardware platform which takes EP2C35F484C8chip as the core device.