.2.8 V, 25mhz, 10-bit Analog-to-digital Converter Design

The thesis presents the design of a 2.8V 25MHz 10-bit pipeline Analog-to-Digitalconvert, using a 1.5bit/stage pipeline ADC with 9 stages.The folded-cascode amplifier is adopted, in order to acquire large range of outputswing and input common mode voltage, as well as high-gain. Programmable gainamplifier used in the S/H results in bigger range of the input signal, and negativesignal can never be sampled with the offset voltage connected. The dynamiccomparators which are lack of kickback noise keep the analog signal from pipelinestage stable during the high frequency sampling phase. In clock generating circuit,two-stage differential inverter is used to generate two-phase non-overlapping clock.D-flip-flop used in the digital delay block, more accurate delay is achieved. Digitalcorrection logic accomplished perfectly make use of the simple adder unit.Adopting the SMIC 0.35μm technology, all simulations are carried out byHSPICE. Under the condition of TT comer 25℃, amplifier's direct current gain isas high as 78dB, and its bandwidth is 470MHz. Also the S/H block and MDAC blockmeet the requirement of precision, except of good linearity, and the Analog-to-Digitalconvert works well.