Based On Random Logic, The A / D Converter Design

A new method of indirect analog-to-digital convertion based on stothcastic logic is given in this paper. First, digital signal is converted to a stochastically coded pulse sequences. Information is represented by the statistical mean value of the pulse sequences.In a binary logic, it is the probability of taking a "high" level, at a given clock cycle.If the stream of pulses is filtered using a low pass filter, its DC component can be obtained.In this way, digital-to-analog convertion based on stochastic logic can be implemented.Then according to the method used in the mixed circuit designs, stochastic analog-to-digital convertion can also be realized. The stochastic DAC (sDAC) designed in this paper uses all digital circuits except a resistor and a capacitor. On the basis of sDAC, the sADC can be implemented, only by adding an analog comparator. It is something like what people called "quasi-digital" ADC. According to a certain researches on the stochastic logic systems, the existing algorithem is improved and a new algorithm which is simpler and easier to understand is presented.At last, the paper gives out the best circuit architecture to generate stochastic logic pulse sequences.A hardware verification circuit board for the quasi-digital sADC circuits based on FPGA chip is given. FPGA is more suitable in terms of both economical and design period. In addition, it has many more merits such as flexible configuration, easy upgraded, shorter design cycle, and low cost, low risk and so on. The main purpose of designing the board is to verify the correctness of the algorithm proposed in this paper and find more problems when design such similar systems. EDA, VHDL and top-down design method are all used in the system design. The sADC system that is implemented in an FPGA chip EPF10K10TC144 is 8 bits resolution and the dynamic range of the input analog voltage is between 0.0V and 5.0V.