The Design Of 622Mb/s High Speed Demultiplexer In 0.6μm CMOS Technology

Demultiplexer is one of the key electronic components in optic-fiber transmission systems.It normally lies at the end of optic-fiber recerver,which recovery original low-speed signals from a high-speed signal.In this thesis,we discuss the circuit design techniques,the technology of the IC realization and principal of multiplexer and demultiplexer in transmission systems.Three basic strctures for demultiplexer,i.e.serial,parallel and tree.Their working principal,advantages and disadvantages will be discussed in the thesis.According to their characteristics and the design objective.the tree architecture was selected.Circuit design is the basis of design of demultiplexer.Speed,power and chip area are the main factors that should be considered in circuit design.Every circuit structure has its merits and drawbacks,e.g.CMOS logic family has a slower speed,but lower power,smaller area,SCFL (Source Couple FET Logic) family has a higher speed,but higher power,larger area.We should choose a proper circuit structure or their mixed structure for certain design to get a good tradeoff among the three factors.Flip-flop is the fundamental element of demultiplexer,setup time and hold up time are key factors,which influence the speed of circuit,thus the design aim is how to reduce them.In this thesis we place emphasis on the design of SCFL latches.Layout design is discussed briefly and simulation results are presented.At last,the test results from the relatived demultiplexer IC on wafer,will be domestrated and analysed.Demultiplexer was fabricated in CSMC-HJ 0. 6um CMOS Technology.The test results show that demultiplexer accomplished the function in SDH STM-4 speed level.Furthermore,it can reach 622Mb/s data speed.