Ultra-high-speed 0.18¦Ìm Cmos Multiplexer Integrated Circuit Design

Data multiplexers are key blocks in high-speed data communication systems and essential components of serial links. The ever-increasing demand for bandwidth has led to serial communication data rates over multi-Gb/s. System integration, lower cost and lower power requirements in optic-fiber transmission system have made the CMOS the technology of choices for high-speed multiplexing. The main work of the thesis is research and design of high-speed CMOS multiplexer IC. System design, structure selection, circuits design, optimization of components parameters and layouts design are my work stress.A 10Gb/s 4-to-1 multiplexer IC for high-speed operation is presented in this paper. The IC is fabricated in a 0.18μm standard bulk CMOS technology and uses 1.8V supply voltage. Tree topology and SCFL circuits are used because of the higher speed compared to static CMOS and the robustness against common-mode disturbances. Tree-type structure decreases the speed of most modules, which makes design easier, and decreases the power consumption. Improved parallelism-type structure was used in 2:1 serial links to obtain relaxed timing condition and to eliminate clock skew. The difference between the phases enter the 2-bit selector is adjusted by a master-slave flip-flop, a master-slave-master flip-flop and several buffers in these units. Furthermore, in order to avoid clock skew familiar in high-speed sequential logic circuits, negative clock skew system is used in clock routeway and buffers are placed in clock-tree.The half-rate architecture is adopted to reduce the complexity of clock design and save power. Inductive shunt peaking with active inductors is used to enlarge the bandwidth of selectors.The simulation results show that the MUX works up to 13.5 Gb/s and consumes about 313mW, and it amplifies the input differential signal amplitude from 400mV to small less than 400mV. Measurement results show the performance of the divider. Its size is about 0.97×0.88mm~2.