High Speed Multiplexer With PLL For 100G Ethernet

With the rapid expansion of data traffic demand in the era of big data,the application of 100 G or even 400 G Ethernet is becoming more and more widespread.As 100 G technologies and standards become more sophisticated,data centers around the world are accelerating the construction of 100 G networks.100 G Ethernet is an Ethernet standard promulgated by the IEEE.802.3ba working group.The main function of the PMA sublayer of the physical layer is to realize N:1 multiplexing to adapt to the electrical or optical devices of the PMD sublayer.A feasible electrical interface scheme is a 4×25G scheme.Therefore,the research on the design of 100 G Ethernet high-speed multiplexer and phase-locked loop has important practical significance and application value.The research of this article is carried out from this,the main contents are as follows:25Gb/s 4:1 high-speed MUX circuit design.Discuss the 4:1 MUX design method and ideas in the case of high output rate,mainly on the issues of accuracy and power consumption.For the low-speed module of the circuit in the MUX,a CMOS circuit with lower power consumption is used,which is in transmission accuracy.For consideration,the high-speed module of the circuit is designed with SCFL structure to reduce power consumption as much as possible under the premise of satisfying transmission.The output clock is 12.5GHz PLL circuit design.A Type-II phase-locked loop circuit is designed to provide a high-speed clock frequency for the MUX circuit.The VCO adopts the traditional cross-coupled LC structure to obtain lower phase noise and power consumption.The frequency divider is composed of flip-flops.The circuit leads to the output signal of the frequency divider 2 and provides 6.25 G clock frequency as the low-speed clock of the MUX circuit..This paper completes the layout design and post-simulation of the entire MUX circuit and PLL.The layout area(including pads)is 925?m×840?m.The post-simulation results show that 4 channels of 25Gb/s data signals are transmitted through the MUX circuit.It can accurately reach the output end,the horizontal opening amplitude of the eye diagram reaches 0.8UI,the vertical opening amplitude(including pad simulation)reaches200m V,the phase noise of the phase-locked loop VCO is-173 d Bc/Hz,and the jitter of the clock is 0.074 UI,under 65 nm process,the power consumption of the circuit is 252 m W.