Linear Frequency Modulation Pulse Compression System Design And Fpga Implementation

In this thesis, the design and implementation on FPGA methodology for the highspeed and high performance digital pulse compression processor including the systemarchitecture design, algorithm implementation and testing method are presented.In the introduction, the research background and significance are introducedfirstly. Then, the content, the key technology and tendence of radar digital pulsecompression are presented. The requirement for the design and realization of digitalpulse compression system id stated. Lastly, main work of the thesis is introduced.In chapter 2, the fundamental theory about pulse compression of LPM signal isintroduced. A real-time proof on the system implementation method is given. Ananalysis simulatied in MATLAB is given here.In chapter 3, system is consisted of three parts, such as input part, pulsecalculation part and output part. Their functions to be implemented are introducedrespectively in the form of diagram.In chapter 4, the methods of realizing digital pulse compression are summarized.Then a systematic study on the key technology of implementing digital pulsecompression is carried out. A self-defined floating_point data and time-dividedbutterfly arithmetic unit are presented to get good performance.In chapter 5, I/O module function is described in detail.In chapter 6, single and united verification strategy are presented.ImplementVHDL coding debug between MATLAB and Modelsim using Link for Modelsimtools.SOC testing is also completed using ChipScope. The tested result about pulsecompression processor is proved to be true, meets systematic demands.The system is realized with large dynamic range, high precision, light weight,short processing time, small bulk and power. The system is also tested the highperformance and practicability on signal process of modern radar.