Target Recognition Radar Frequency Domain Pulse Compression Technique Fpga Design

Pulse compression radar signal deal with the echo signal which is launched by radar, associated with strong anti-interference ability and effectively solute the conflict between the radar range and distance resolution, it is the main method which can realize high-resolution radar.Optional DSP device programmed by software to achieve pulse compression algorithm not only slowly, delay big, and efficiency is not high. Hardware realization of pulse compression pulse compression system can reduce power consumption and enhance improve its capacity. Based on FPGA devices, using VHDL and Verilog HDL hardware description language, realize the LFM digital pulse compression by the way of frequency-domain, including system architecture design, program improvements, verification and simulation, algorithm implementation and testing.In this thesis first clarified the research background and significance, summarized the key technology and tendence of radar digital pulse compression.,introduced the requirement for the design and realization of digital pulse compression system; introduced the fundamental theory about pulse compression of LFM signal and phase code signal. and compared the performance of LFM signal and phase code signal realize digital pulse compression.and simulatied the system in MATLAB; system is consisted as input part, pulse compression part and output part.and implemented their function in the form of diagram; introduced floating point data format, use standard floating-point data format to achieve pulse compression design, and give a detailed description of the design and implementation of the various parts of pulse compression by modules; summarized the methods of realizing digital pulse compression. improvement of pulse compression system, using time-multiplexing butterfly design idea to improve the structure of digital pulse compression, and using self-defined floating-point format, pipeline structure, ping-pong and improved storage radix-2 butterfly computing unit, the design of processing by the butterfly unit, address generator and control unit to improve effective data dynamic range and precision, the design can be extended into the realization of any of the 2N-point FFT computation; using the Joint simulation methods of MATLAB and QuartusII tested the function of the pulse compression system, and compare the performance of the two methords ,which used to design the system, shows the correctness of the design.This article discusses the digital pulse compression system,which has the merits of large dynamic range and high accuracy. For high-performance modern radar signal processing system provides a reference design.