Pulse Compression Of Large Time-Bandwidth Product Signals And Optimal Realization Architecture

High-resolution radar is the development trend of modern radar, and in order to obtain high range resolution and the wide role of distance, pulse compression of large time-bandwidth product signals is needed. However, as the time-bandwidth product increasing, the number and the speed of signal processing's operations is increasing sharply, the traditional architecture and device is difficult to accomplish it. FPGA which is advanced in parallel processing can be a good solution to this problem.Based on the analysis of the principle of LFM signal's pulse compression and ultra-low sidelobe technologies, this paper studied the implementation of large time-bandwidth product signal's pulse compression based on FPGA. LFM signal's pulse compression is implemented by FIR filter, and this paper presents two high-speed FIR filter implementation structure: polyphase filter architecture and distributed parallel architecture. the former extracted the filter's results to bring the speed down. And the latter reduced the speed by increasing the number of multipliers. Using it, the maximum bandwidth of pulse compression is no longer limited by multiplier's speed .In order to reduce the number of multipliers, simplified architecture and multi-level distributed parallel architecture is presented.Parallel architecture will increase the number of multiplier. In order to solve the problem which the number of multiplier in FPGA is limited, so some implementations of high-speed multiplier based on FPGA are recommended, such as Distributed LUT, CSD and building multipliers by logic resources. According to Distributed LUT's characteristics, time division multiplexing and data preprocessing are proposed to reduce more resource's consumption. Finally, polyphase filter and two-level distributed parallel FIR filter based on distributed LUT are achieved.