Research And Development Of The High Performance Full Custom 64-bits Parallel Integral Multiplier

Multiplier is one of the most important components in microprocessor.The speed and power dissipation of 64-bits parallel integer multiplier have great effect on the performance of the 64-bits microprocessor.This thesis presents a lot of correlative techniques about the parallel integer multiplier.Meanwhile,a 64-bits parallel integer multiplier with high performance is realized in full custom design methodology.This thesis mainly contributes to the following topics:1.An improved 64-bits parallel integer multiplier algorithm is discussed and verified.The proposed algorithm adopts the idea of combining modified value.Based on the algorithm,the architecture of 64-bits parallel integer multiplier is proposed and verified at RTL HDL.2.Considering the delay in critical path,the critical module circuit is optimized with logic restructing and logic structure sharing.3.In circuit design,the cell circuits on critical path is optimized for high performance.Transmission gate circuits,whose performance is better than others,are used in most cells.The circuits' parameters are obtained by manual computation and Hspice simulation.4.The wire delay is firstly taken into account in layout design.By well-connected floorplanning,cell layout design,part layout connection and whole layout connection, the layout of 64-bit parallel integer multiplier is finally realized.The layout area of the multiplier is 1.67mm~2.In typical condition,the delay of the critical path is 2.4ns,and average power dissipation is 239.4mW.The design achieves the goal of high speed,low power dissipation and small area.5.The test scheme about parallel integer multiplier is proposed.Considering the difficulty of chip test,a boundary scanning test method is adopted and the layout of multiplier with scanning chains is taped out.6.The design methodology of the 64-bits parallel integer multiplier IP core is studied.