The Full-custom Design And Implementation Of High-performance DSP Hard Core

Since its development,Field Programmable Gate Array(FPGA)has become a typical representative of reconfigurable digital processing unit due to its advantages of short development cycle,low cost and high flexibility.It has been widely used in popular field such as image processing,artificial intelligence and signal transmission.As an important functional part of FPGA,the embedded Digital Signal Processing(DSP)module undertakes most of the operation tasks for high speed and complex algorithm digital signal processing.Therefore,in order to further improve the performance of FPGA,it is particularly important to design a high-performance DSP Intellectual Property core(IP core)with fast computing speed and abundant algorithms.This thesis explored the basic architecture of FPGA and its advantages as a digital signal processing unit,studied the characteristics of multiple types of IP cores.Thought analyzed the mainstream commercial embedded DSP hard core and the recent achievements of colleges and universities at domestic and overseas.The study found that none of the products in the 28nm process could reach the maximum operating frequency to more than 741MHz,which limited the ability of the system processing high speed digital signals.In order to further improve the computing speed of embedded DSP hard core,starting with the core modules of embedded DSP,adders and multipliers,the relevant research was studied to select the suitable schemes.According to the function of the embedded DSP hard core and the high-speed computing requirements,the overall structure was determined.In order to reduce the number of partial products and improve the compression efficiency,the optimized radix-4 Booth algorithm and the Wallace tree compression structure were adopted in the multiplier.The arithmetic logic unit could perform basic arithmetic and logic operations.Based on the high speed of operation and the design requirements of Single Instruction Multiple Data(SIMD)mode,the structure of addition was made by the combination of carry select adder and carry look-ahead adder.Embedded optional registers to achieve the pipeline function was helpful to improve the throughput and the processing speed of hard core.The reserved cascade port facilitated the connection of adjacent DSP hard cores,which increased the flexibility of the structure.The multiplexer group configured by the external signal could form a combination of various operands.A pattern detector joined in the DSP hard core could detect the pattern of output data,which assisted enriching more functions.With full-custom design in GF 28 nm CMOS process,the high performance DSP hard core was achieved in schematic and layout.The simulation results indicate the maximum operating frequency can reach1.0GHz at 1.0V,25?.The area of it cost is 0.0112 mm~2.This embedded DSP hard core can be applied in FPGA to achieve more functions and greater computing power.The main research achievements are summarized as follows:(1)Compared with the traditional method,the array regularity was improved,the area consumption was reduced,and it could be benefit for the faster compression by using the modified radix-4 Booth algorithm based on a 3 bits code generating partial product,optimizing least-significant bit generating circuit and employing uniform operations to extend the sign bit of each partial product.(2)A basic compressor with only 12 transmission gates and dual-rail output was achieved by full customization.On the basis,various types of basic compressors were optimized and combined into high-order compressors.Composed of these compressors,the Wallace tree compressing 9 groups of partial product to 2 groups only needs three-stage compression and 8XOR-delay in critical path,which improved the compression efficiency and reduced the number of unbalanced paths.