Optimization Of A 64-bit High Performance Float-point Multiplier

The performance of float-point multiplier is the bottleneck for the high performance microprocessor, because the architecture of float-point multiplier is very complex, and its latency of the circuit-implement is especially long. Optimize the speed of the implementation of float-point multiplier is very importment for the improvement of microprocessor. Semi-custom design can't satisfy the more and more high frequency. In order to get to the target, partial product compression and accumulation is designed by full-custom. Optimizing the float-point multiplier by the method of combination of full-custom and semi-custom is effective.The fruit of studying is that:1. A novel 4-2 compressor is proposed in this paper is used in the compression, the latency is less 27.5 percentage than original 4-2 compressor;2. The latency of the 4-2 compressor designed by full-custom is 0.11ns, and the latency of the 4-2 compressor designed by semi-custom is 0.18ns. The latency of the 4-2 compressor designed by full-custom is less 39 percentage than the 4-2 compressor designed by semi-custom;3. Analyze the related the number of bit of team adder with latency of carry tree to give the method of implementing high speed 136-bit adder by all parallel no matter the Sum or Carry. And designed by full-custom, the latency is 0.30ns, making the latency of the partial product accumulation be less 21.3 percentage than that semi-custom.The synthesized frequency of optimized float-point multiplier is 1.8GHz based on 65nm technology, which increase 30 percentage than 1.4GHz designed by semi-custom. Physical design the float-point multiplier, and after placing and routing the frequency is 1.36GHz.