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.stm-1/vc-4 The Design Of High-end Multiplexer

Posted on:2007-04-27Degree:MasterType:Thesis
Country:ChinaCandidate:Q GuoFull Text:PDF
GTID:2208360185483054Subject:Circuits and Systems
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SDH (Synchronous Digital Hierarchy) is a new transmission mode. Owing to their major advantages such as high flexibility and manageability, SDH networks have become the backbone of communication networks. Because of the complexity of SDH, ASIC is the trend of the evolution. Now in our country, the key chips of homemade communication devices are still mainly imported. Therefore, a fast improvement of the research and development of SDH ASIC is vital to making our country competitive in the field of communications.This paper begins with the brief introduction of SDH fundamental, mainly including the frame structure of STM-N and the procedure of PDH tributary signal being multiplexed into STM-N frame. Then, a flexible architecture is introduced for implementing SDH STM-1 Add/Drop Multiplexer (ADM). This system architecture is mainly divided into STM-1 /VC-4 high level multiplexer, digital cross-connection and VC-4/E1 mapping system. This subject focuses on the ASIC design of the STM-1 /VC-4 high level multiplexer, which can implement VC-4 add/drop to/from STM-1 buses. The system design of STM-1/VC-4 high level multiplexer is presented, with the construction of the system and the function of each module in the system. In addition to STM-1 frame alignment, the system parallelly scrambles and descrambles STM-1 signal, provides pointer generation and interpretation, and performs payload insertion and recovery. Section overheads are extracted and inserted. Alarm signals are detected and reported, and performance monitoring at various layers is also performed.Top-down design methodology is adopted. After the design partition, the design of each module is finished with Verilog HDL. The function simulation of the design is accomplished with VCS of Synopsys Corp. All the designs are synthesized, that is the design can be synthesized into a manufacturable circuit by the synthesis software Design Compiler of Synopsys Corp. The FPGA verification of the key modules is developed in the platform of Altera FPGA device EP1C6T144C8 (Cyclone series).The focus is kept on some critical points in the modules: the frame aligner of receiver,...
Keywords/Search Tags:SDH, ASIC, Verilog HDL, digital multiplexing, ADM
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