The Design And Implementation Of SDH Digital Cross-Connect System

These years, with the further development of communication and network technologies, multimedia communication, such as the transmission of vioce, data and pictures, has becomes a research hotspot. The throughput of data transmission service increases exponentially, so it requires the communication transmission systems providing much enhanced data progressing ability and capacity. At the same time, SDH network has to accommodate its complexity and performance to data transmission service. As one of the most key parts of SDH transmission system, SDH digital cross-connect equipment have mutiple functions, such as multiplexing, connection layout, protection/recovery, realtime check and control and network management. The performance of SDXC has great effect on the whole optic communication, and is considered as an important performance guidline of SDH transmission equipment capabilities.Firstly this paper introduces the basic knowledge of SDH, including the main characteristic of SDH, frame structure of STM-N frame, multiplexing principle and equipment constitutition. Then the SDXC system is introduced briefly. Basde on this, this paper discusses the functional modules partition of the SDH digital cross-connect system, then presents the design route map, general design scheme and the simulation environment of the whole design. Primarilythe fundamental and design method of main modules in SDXC system are presented in detail.Verilog HDL and Top-Down design methodology are adopted in this design. The function simulation of the design is accomplishded with Xilinx ISE 9.1i design environment, ModelsimXE, and is synthesised by XST software. The FPGA verification of the key modules is developed in the platform of Xilinx FPGA device Spartan 3E X3C500E-4FG320.This paper introduces the design principle of a TU-12 level SDXC matrix used in 155MHzbith SDH optical transmission system. The SDXC matrix is implemented with Field Programmable Gate Array (FPGA). The paper introduces systemic the SDXC, the paralleling scramble and descramble of the data, the pointer interpretation technology and the frame aligner technology. The focus is kept on the design fundamental of the time-slot control module of the SDH cross connect matrix. So it can be used more abroadly. It discusses paralleling digital correlator design method , which is based on flow line, to meet the require of SDH ASIC. And it also discusses the pointer interpretation design method , which is based on states, after analysing the pointer fundamental.