Design And Realization Of A Digital Filter Based On C And Verilog HDL

This thesis is mainly based on basic principles and commonly used architectures of digital filter. After familiar with the traditional ASIC and be able to use the Verilog HDL to design digital filter, study higher levels of C-to-RTL ASIC design, and use the Catapult C Synthesis algorithm synthesis tool to design digital filters. Then compare two different methods in different ways, and analyze the pros and cons of them.Nowadays, Verilog and VHDL languages have been used widely in the design of traditional ASIC design, and then use the integrated development environment synthesize the RTL codes to get the hardware circuit. By this method, engineers can devide their designs into several different levels of modules which can describe the designers’ideas by top-down way. Then by using the EDA tools, the design should be simulated and verified. And combine necessary modules, convert them into gate-level netlist with logic synthesis tools. Finally, we can get the files of layout and complete the design work by using the physical synthesis tools and the technology library provided by semiconductor foundry, in this process we need some constraints like area and timing.With the constant expansion of digital integrated circuits, and the algorithm complexity is increasing. Traditional RTL design methodology has reached its limit. Due to the traditional development cycle is longer, and manual codes are error-prone, the pressure in all aspects makes the engineers cannot get the optimal solution in a short period of time. Therefore, there is the urgent need of a new design method, which can translate complex algorithms that described by high-level languages into RTL codes that described by HDL languages directly.Catapult Synthesis tools set the design up to the higher level:ANSI C++making the need in the next generation of wireless, satellite, video and other applications of complex high performance ASIC and FPGA hardware rapidly realize possible. Catapult is the industry’s first product with standard ANSI C, it avoids the possible errors introduced by manual coding, and can automatically generate high-quality RTL code, with the speed faster than other methods. And meanwhile, it can compare different designs architecture to find out the best compromise between performance, area and power in a short time.This paper willl use these two methods to complete the same kind of digital filter The mainly contents include:theory of filter, C and Verilog HDL coding, Modelsim simulation, Catapult C synthesis, Design Compiler synthesis. And finally, with a methodological point of view, the results achieved by the two design methods will be compared and thus point out the pros and cons of the two methods.