Viterbi Decoder In An Fpga, The Low-power Research

Through the development of the modern correspondence, people has more and more requests in credibility and the usefulness that the information delivery. The Viterbi algorithm has been widely used, convolution code is very popular, so how to improve the performance and reduce the power and area of the decoder is an important thing. Specifically due to their forward error correction capability, the Viterbi decoder has often been used in digital communication system such as satellite communication systems, GSM, 3G, DVB and ATSC.The thesis mainly includes designing on the Viterbi decoder, based on the FPGA, and further in low power consume of the Viterbi decoder. At first, the basic principle about convolutional code and Viterbi decoding algorithm are introduced. After that,we introduce some classic agorithms about the realization of a low power Viterbi decoder. Finally, design a modified Register Exchange and bit-serial ACS architecture (3,1,9) low power Viterbi decoder. Quartus II is applied as the simulation tool. The effects of the time sequence netfist simulation of the circuit and FPGA verification indicate the correctness of the circuit design.According to the analysis that imitates a true result, the characteristic of the designed low power consume Viterbi decoder fits together mutually with theories analysis.