Viterbi Decoder Fpga Implementation

Convolutional Encoding is one of encoding methods commonly used in the deep space communication systems and the wireless communication systems. Viterbi decoding algorithm is a kind of maximum likelihood decoding algorithm of convolutional code, according to the maximum likelihood decoding standard to find out a maximum likelihood path to get the decoding result in the trellis chart. This paper mainly details the implementation of the 3-bits soft-decision Viterbi decoder which makes use of FPGA, the design is realized by VHDL, and is compiled and simulated in Modelsim and Quartus Ⅱ. In this paper, many kinds of algorithm of the modules of the Viterbi decoder is described, and the specific realized method used in this design is specially described, and the correctness of the design is tested and verified through the simulation and the test. At last the development and the application of the Viterbi decoder in the future communication systems is described.